View AD7738_1090790.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 AD7738 8-channel, high throughput, 24-bit - adc features high resolution adc 24 bits no missing codes 0.0015% nonlinearity optimized for fast channel switching 18-bits p-p resolution (21 bits effective) at 500 hz 16-bits p-p resolution (19 bits effective) at 8.5 khz 15-bits p-p resolution (18 bits effective) at 15 khz on-chip per channel system calibration configurable inputs 8 single-ended or 4 fully differential input ranges +625 mv, +1.25 v, +2.5 v, 625 mv, 1.25 v, 2.5 v 3-wire serial interface spi?, qspi?, microwire? and dsp compatible schmitt trigger on logic inputs single-supply operation 5 v analog supply 3 v or 5 v digital supply package: 28-lead tssop applications plcs/dcs multiplexing applications process control industrial instrumentation functional block diagram sclk din dout cs rdy reset serial interface control logic ain4 ain5 ain6 ain7 mux aincom/p0 ain0 ain1 ain2 ain3 dgnd dv dd reference detect refin?refin+ i/o port sync/p1 clock generator mclkin mclkout muxout adcin a gnd av dd 24-bit - adc bu ffer AD7738 calibration circuitry general description the AD7738 is a high precision, high throughput analog front end. true 16-bit p-p resolution is achievable with a total con- version time of 117 s (8.5 khz channel switching), making it ideally suitable for high resolution multiplexing applications. the part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to a 15.4 khz. the analog front end features eight single-ended or four fully differential input channels with unipolar or bipolar 625 mv, 1.25 v, and 2.5 v input ranges and accepts a common-mode input voltage from 200 mv above agnd to av dd ?300 mv. the multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before applying the input to the adc. the differential reference input features ?o-reference?detect capability. the adc also supports per channel system calibra- tion options. the digital serial interface can be configured for 3-wire opera- tion and is compatible with microcontrollers and digital signal processors. all interface inputs are schmitt triggered. the part is specified for operation over the extended industrial temperature range of ?0 c to +105 c. other parts in the AD7738 family are the ad7734 and the ad7732. the ad7734 analog front end features four single-ended input channels with unipolar or true bipolar input ranges to 10 v while operating from a single 5 v analog supply. the ad7734 accepts an analog input overvoltage to 16.5 v while not degrading the performance of the adjacent channels. the ad7732 is similar to ad7734, but its analog front end features two fully differential input channels. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation
rev. 0 C2C AD7738?pecifications parameter min typ max unit test conditions/comment adc performance chopping enabled conversion time rate 372 12190 hz configure via conversion time register no missing codes 1 24 bits fw 6 (conversion time 165 s) see typical performance characteristics output noise see table i resolution see tables ii and iii integral nonlinearity (inl) 0.0015 % of fsr ain range = 2.5 v 0.0015 % of fsr ain range = 1.25 v offset error (unipolar, bipolar) 2 10 v before calibration offset drift vs. temperature 1 280 nv/ c gain error 2 0.2 % before calibration gain drift vs. temperature 1 2.5 ppm of fs/ c positive full-scale error 2 0.2 % of fsr before calibration positive full-scale drift vs. temperature 1 2.5 ppm of fs/ c bipolar negative full-scale error 3 0.0030 % of fsr after calibration 3 common-mode rejection 80 100 db at dc, ain = 1 v power supply rejection 70 80 db at dc, ain = 1 v adc performance chopping disabled conversion time rate 737 15437 hz configure via conversion time register no missing codes 1 24 bits fw 8 (conversion time 117 s) see typical perfomance charateristics output noise see table iv resolution see tables v and vi integral nonlinearity (inl) 0.0015 % of fsr offset error (unipolar, bipolar) 4 1m v before calibration offset drift vs. temperature 1.5 v/ c gain error 2 0.2 % before calibration gain drift vs. temperature 2.5 ppm of fs/ c positive full-scale error 2 0.2 % of fsr before calibration positive full-scale drift vs. temperature 2.5 ppm of fs/ c bipolar negative full-scale error 3 0.0030 % of fsr after calibration 3 common-mode rejection 75 db at dc, ain = 1 v power supply rejection 65 db at dc, ain = 1 v analog inputs analog input voltage ranges 1, 5 2.5 v range ?.9 2.5 +2.9 v +2.5 v range 0 0 to 2.5 2.9 v 1.25 v range ?.45 1.25 +1.45 v +1.25 v range 0 0 to 1.25 1.45 v 0.625 v range ?25 625 +725 mv +0.625 v range 0 0 to 625 725 mv ain, aincom common-mode voltage 1 0.2 av dd ?0.3 v ain, aincom input current 6 200 na only one channel, chop disabled ain to muxout on resistance 1 200 ? reference input refin(+) to refin(? voltage 1, 7 2.475 2.5 2.525 v noref trigger voltage 0.5 v noref bit in channel status register refin(+), refin(? common-mode voltage 1 0av dd v reference input current 8 400 a system calibration 1, 9 full scale calibration limit +1.05 fs v zero scale calibration limit ?.05 fs v input span 0.8 fs 2.1 fs v (?0 c to +105 c, av dd = 5 v 5%, dv dd = 2.7 v to 3.6 v or 5 v 5%, refin(+) = 2.5 v, refin(? = 0 v, aincom = 2.5 v, muxout(+) = adcin(+), muxout(? = adcin(?, internal buffer on, ain range = 1.25 v, f mclk = 6.144 mhz; unless otherwise noted.)
rev. 0 AD7738 ?3? parameter min typ max unit test conditions/comment logic inputs sclk, din, cs reset c c cs cs dd r c t d dd t d dd t t d dd t d dd t d dd t t d dd cn c c n d dd n d dd n d dd n d dd ctts ct dt rdy sn d dd srce d dd sn d dd d dd srce d dd sc sc nt rs c n dd n dd tt sn t c dd sn t c dd sn t c dd srce dd werrereents dd nd d dd dnd dd cn dd dd c dd d dd cn d dd d dd cn d dd dd d dd cs dd d dd dn w ds w dd d dd ntes s scsc sstns sdcssccssc tntrcdc nrrcscd c s ts re d tctcs wcctcds ecnd dd dd dd dd s
rev. 0 ?4? AD7738 timing specifications 1, 2, 3 (av dd = 5 v 5%; dv dd = 2.7 v to 3.6 v or 5 v 5%; input logic 0 = 0 v, logic 1 = dv dd unless otherwise noted.) parameter min typ max unit test conditions/comment master clock range 1 6.144 mhz t 1 50 ns sync reset redertn cs escest scedd d dd d dd cs edd d dd d dd sc sc cs rescret rtscre wrteertn cs esces dscrest dscret sc sc cs rescret ntes s d dd s t tcssc t tt s
rev. 0 AD7738 ?5? dout msb t 5 t 9 lsb t 5a cs t 7 t 8 t 6 t 4 sclk figure 1. read cycle timing diagram din msb t 12 lsb t 13 sclk cs t 15 t 16 t 14 t 11 figure 2. write cycle timing diagram to output pin 50pf i sink ( 800 a at dv dd = 5v 100 a at dv dd = 3v) 1.6v i source ( 200 a at dv dd = 5v 100 a at dv dd = 3v) figure 3. load circuit for access time and bus relinquish time
rev. 0 ?6? AD7738 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7738 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * (t a = 25 c unless otherwise noted.) av dd to agnd, dv dd to dgnd . . . . . . . . . e0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . . . . e5 v to +5 v ain, aincom to agnd . . . . . . . . . e0.3 v to av dd + 0.3 v refin(+), refin(e) to agnd . . . . . e0.3 v to av dd + 0.3 v muxout(+) to agnd . . . . . . . . . . . e0.3 v to av dd + 0.3 v muxout(e) to agnd . . . . . . . . . . . e0.3 v to av dd + 0.3 v adcin(+), adcin(e) to agnd . . . . e0.3 v to av dd + 0.3 v p1 voltage to agnd . . . . . . . . . . . . . . e0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . . e0.3 v to av dd + 0.3 v digital output voltage to dgnd . . . . e0.3 v to av dd + 0.3 v operating temperature range . . . . . . . . . . e40 c to +105 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c tssop package, power dissipation . . . . . . . . . . . . . 660 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 97.9 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. sclk din dout cs rdy reset serial interface control logic ain4 ain5 ain6 ain7 mux aincom/p0 ain0 ain1 ain2 ain3 dgnd dv dd reference detect refine refin+ i/o port sync /p1 clock generator mclkin mclkout muxout adcin a gnd av dd 24-bit - adc bu ffer AD7738 calibration circuitry dv dd av dd figure 4. block diagram ordering guide temperature package package model range description options AD7738bru e40 c to +105 ct ssop 28 ru-28
rev. 0 AD7738 ?7? pin function description pin no. mnemonic description 1 sclk serial clock. schmitt-triggered logic input. an external serial clock is applied to this input to transfer serial data to or from the AD7738. 2 mclkin master clock signal for the adc. this can be provided in the form of a crystal/resonator or external clock. a crystal/resonator can be tied across the mclkin and mclkout pins. alternatively, the mclkin pin can be driven with a cmos compatible clock and mclkout left unconnected. 3m clkout when the master clock for the device is a crystal/resonator, the crystal/resonator is connected between mclkin and mclkout. if an external clock is applied to the mclkin, mclkout provides an inverted clock signal or can be switched off to lower the device power consumption. mclkout is capable of driving one cmos load. 4 cs cssw dscdndt cs reset st e reset dd snd nc ctdtd t wd sync sync ddtd wsynce sync d tw nn t t n ncnrtn tew ns d sc dnd cn d dd ct dn cs dt reset rdy dd nd nc ren sync ren n n n n n n n n t dcn t dcn
rev. 0 ?8? AD7738 pin function description (continued) pin no. mnemonic pin description 15 adcin(e) adc negative input. in normal circuit configuration, this pin should be connected to the muxoute pin. 16 adcin(+) adc positive input. in normal circuit configuration, this pin should be connected to the muxout+ pin. 21 refin(+) positive terminal of the differential reference input. refin+ voltage potential can lie any where between av dd and agnd. in normal circuit configuration, this pin should be connected to a 2.5 v reference voltage. 22 refin(e) negative terminal of the differential reference input. refine voltage potential can lie any where between av dd and agnd. in normal circuit configuration, this pin should be connected to a 0 v reference voltage. 23 agnd ground reference point for analog circuitry 24 rdy rdy sdd dt s dt d c dn sds dd c d dd dsn dnd rdc
rev. 0 AD7738 ?9? output noise and resolution specification the AD7738 can be operated with chopping enabled or disabled, allowing the adc to be programmed either to optimize the throughput rate and channel switching time or to optimize offset drift performance. noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times. chopping enabled the first mode, in which the AD7738 is configured with chopping enabled (chop = 1), provides very low noise numbers with lower output rates. tables i to iii show the e3 db frequencies and typical performance versus channel conversion time or equivalent o utput data rate, respectively. table i shows the typical output rms noise. table ii shows the typical effective resolution based on t he rms noise. table iii shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. the peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise. these typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 v and mclk = 6.144 mhz. the conversion time is selected via the channel conversion time register. table i. typical output rms noise in v vs. conversion time and input range with chopping enabled conversion conversion output e3 db input range time time data rate frequency fw register ( s) (hz) (hz) 2.5 v, +2.5 v 1.25 v, +1.25 v, 625 mv, +625 mv 127 ffh 2686 372 194 1.8 1.1 46 aeh 999 1001 521 3.0 1.8 17 91h 395 2534 1317 5.1 3.0 8 88h 207 4826 2510 8.1 4.5 4 84h 124 8074 4198 9.3 5.3 2 82h 82 12166 6326 17.0 10.6 table ii. typical effective resolution in bits vs. conversion time and input range with chopping enabled conversion conversion output e3 db input range time time data rate frequency fw register ( s) (hz) (hz) 2.5 v +2.5 v 1.25 v +1.25 v 625 mv +625 mv 127 ffh 2686 372 194 21.4 20.4 21.1 20.1 20.1 19.1 46 aeh 999 1001 521 20.6 19.6 20.4 19.4 19.4 18.4 17 91h 395 2534 1317 19.9 18.9 19.6 18.6 18.6 17.6 8 88h 207 4826 2510 19.2 18.2 19.0 18.0 18.0 17.0 4 84h 124 8074 4198 19.0 18.0 18.8 17.8 17.8 16.8 2 82h 82 12166 6326 18.1 17.1 17.8 16.8 16.8 15.8 table iii. typical peak-to-peak resolution in bits vs. conversion time and input range with chopping enabled conversion conversion output e3 db input range time time data rate frequency fw register ( s) (hz) (hz) 2.5 v +2.5 v 1.25 v +1.25 v 625 mv +625 mv 127 ffh 2686 372 194 18.4 17.4 18.2 17.2 17.2 16.2 46 aeh 999 1001 521 17.8 16.8 17.5 16.5 16.5 15.5 17 91h 395 2534 1317 16.8 15.8 16.7 15.7 15.7 14.7 8 88h 207 4826 2510 16.5 15.5 16.2 15.2 15.2 14.2 4 84h 124 8074 4198 16.0 15.0 16.0 15.0 15.0 14.0 2 82h 82 12166 6326 15.0 14.0 15.0 14.0 14.0 13.0
rev. 0 ?10? AD7738 chopping disabled the second mode, in which the AD7738 is configured with chopping disabled (chop = 0), provides faster conversion time while sti ll maintaining high resolution. tables iv to vi show the e3 db frequencies and typical performance versus channel conversion time or equivalent output data rate, respectively. table iv shows the typical output rms noise. table v shows the typical effective res olution based on the rms noise. table vi shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. the peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise . these typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 v and mclk = 6.144 mhz. the conversion time is selected via the channel conversion time register. table iv. typical output rms noise in v vs. conversion time and input range with chopping disabled conversion conversion output e3 db input range time time data rate frequency fw register ( s) (hz) (hz) 2.5 v, +2.5 v 1.25 v, +1.25 v, 625 mv, +625 mv 127 7fh 1357 737 671 2.7 1.5 92 5ch 9 92 1008 917 3.0 1.8 35 23h 398 2511 2285 5.1 3.0 16 10 h2 00 4991 2510 7.5 4.5 99 h1 27 7847 7141 10.2 5.9 88 h 117 8545 7776 11.4 6.5 33 h6 5 15398 14013 15.5 10.3 table v. typical rms resolution in bits vs. conversion time and input range with chopping disabled conversion conversion output e3 db input range time time data rate frequency fw register ( s) (hz) (hz) 2.5 v +2.5 v 1.25 v +1.25 v 625 mv +625 mv 127 7fh 1357 737 671 20.8 19.8 20.6 19.6 19.6 18.6 92 5ch 992 1008 917 20.6 19.6 20.4 19.4 19.4 18.4 35 23h 398 2511 2285 19.9 18.9 19.6 18.6 18.6 17.6 16 10 h2 00 4991 2510 19.3 18.3 19.0 18.0 18.0 17.0 99 h1 27 7847 7141 18.9 17.9 18.7 17.7 17.7 16.7 88 h 117 8545 7776 18.7 17.7 18.5 17.5 17.5 16.5 33 h6 5 15398 14013 18.0 16.7 17.8 17.1 17.1 16.1 table vi. typical peak-to-peak resolution in bits vs. conversion time and input range with chopping disabled conversion conversion output e3 db input range time time data rate frequency fw register ( s) (hz) (hz) 2.5 v +2.5 v 1.25 v +1.25 v 625 mv +625 mv 127 7fh 1357 737 671 17.9 16.9 17.8 16.8 16.8 15.8 92 5ch 992 1008 917 17.8 16.8 17.4 16.4 16.4 15.4 35 23h 398 2511 2285 17.0 16.0 16.8 15.8 15.8 14.8 16 10 h2 00 4991 2510 16.3 15.3 16.2 15.2 15.2 14.2 99 h1 27 7847 7141 16.1 15.1 15.9 14.9 14.9 13.9 88 h 117 8545 7776 16.0 15.0 15.7 14.7 14.7 13.7 33 h6 5 15398 14013 15.0 14.0 14.8 13.8 13.8 12.8
rev. 0 t ypical performance characteristicseAD7738 ?11? filter word 25 16 110 2 no missing codes 3456789 24 20 18 17 23 22 19 21 chop = 1 tpc 1. no missing codes performance, chopping enabled filter word 25 16 110 2 no missing codes 3456789 24 20 18 17 23 22 19 21 chop = 0 tpc 2. no missing codes performance, chopping disabled input frequency 0 e180 0 1400 200 gain e db 400 600 800 1000 1200 e20 e100 e140 e160 e40 e60 e120 e80 thd = 115db tpc 3. typical fft plot; input sinewave 183 hz, 1.2 v peak, range 1.25 v, conversion time 394 s, chopping enabled va l u e 140 0 e80 80 e60 number of codes e40 e20 0 20 40 120 40 100 80 20 60 effective res. 19.9 bits p-p res. 17.0 bits 60 tpc 4. typical histogram; analog inputs shorted; range 2.5 v, conversion time 394 s; chopping enabled
rev. 0 ?12? AD7738 table vii. register summary addr dir bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register hex default value communications 00 w 0 r/ w r rw dr dr rdyn sync r r crc cc t rw tr dcs r rdy rdy rdy rdy rdy rdy rdy rdy c rw cr dcsc rw dcscr dcs rw dcsr cd r dr csc rw cscr csc rw cscr cs r c c c rdy nre sn r cn cs rw c c s ene rn rn rn cct rw c ww rw d d d cds d crd c ntes tsc tt dc ts d d d cc sc ds dcssc cssc cssc trs rn rn rn nr
rev. 0 AD7738 ?13? register description the AD7738 is configurable through a series of registers. some of them configure and control general AD7738 features, others ar e specific to each channel. the register data widths vary from 8 bits to 24 bits. all registers are accessed through the communi cation register, i.e., any communication to the AD7738 must start with a write to the communication register, specifying which registe r will be subsequently read or written. communications register 8 bits, write-only register, address 00h all communications to the part must start with a write operation to the communications register. the data written to the commu- nications register determines whether the subsequent operation will be a read or write and to which register this operation wil l be directly placed. the digital interface defaults to expect write operation to the communication register after power on, after reset, or after the subsequent read or write operation to the selected register is complete. if the interface sequence is lost, the part can be reset by writing at least 32 serial clock cycles with din high and cs n rdncr d r w r d t r w s ws st tcccs t c s d n nn n nn n nn n nn n nn n nn n nn n nn
rev. 0 ?14? AD7738 i/o port register 8 bits, read/write register, address 01h, default value 30h + digital input value 40h the bits in this register are used to configure and access the digital i/o pin on the AD7738. bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic p0 p1 p0 dir p1 dir rdy fn 0 0 sync default p0 pin p1 pin 1 1 0 0 0 0 bit mnemonic description 7p 0 when the ai ncom/p0 pin is configured as a digital output, the p0 bit determines the pins output level. 6p 1w hen the p1 pin is configured as an output, the p1 bit determines the pin? output level. when the p1 pin is configured as an input, the p1 bit reflects the current input level on the pin. 5 p0 di rw hen set to 1, the aincom/p0 pin is configured as an analog input. when set to 0, the aincom/p0 pin is configured as a digital output. 4 p1 di rt his bit determines whether p1 pin is configured as an input or an output. when set to 1, the p1 pin will be a digital input; when reset to 0, the pin will be a digital output. 3 rdy fn this bit is used to control the function of the rdy dw rdy w rdy t sync t sync sync wsyncen sync d rr 8 bits, read-only register, address 02h, default value 01h + chip revision 10h bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic chip revision code chip generic code default x x x x 0 0 0 1 bit mnemonic description 7? chip revision code 4-bit factory chip revision code 3? chip generic code on the AD7738, these bits will read back as 01h. test register 24 bits, read/write register, address 03h this register is used for testing the part in the manufacturing process. the user must not change the default configuration of this register. adc status register 8 bits, read-only register, address 04h, default value 00h in conversion modes, the register bits reflect the individual channel status. when a conversion is complete, the corresponding channel data register is updated and the corresponding rdy bit is set to 1. when the channel data register is read, the corresponding b it is reset to 0. the bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being up dated to the channel data register. writing to the mode register resets all the bits to 0. in calibration modes, all the register bits are reset to 0 while a calibration is in progress and all the bits are set to 1 whe n the calibra tion is complete. the rdy dcsrdy rdy rdy rdy rdy rdy rdy rdy rdy d trdycrdyc
rev. 0 AD7738 ?15? checksum register 16 bits, read/write register, address 05h this register is described in the ?d7732/34/38 checksum register?technical note. adc zero scale calibration register 24 bits, read/write register, address 06h, default value 800000h the register holds the adc zero-scale calibration coefficient. the value in this register is used in conjunction with the value in the adc full-scale calibration register and corresponding channel zero-scale and channel full-scale calibration registers to scale digitally all channels?conversion results. the value in this register is updated automatically following the execution of an a dc zero- scale adc self-calibration. writing to this register is possible in the idle mode only. see the calibration description for mor e details. adc full-scale register 24 bits, read/write register, address 07h, default value 800000h the register holds the adc full-scale coefficient. the user is advised not to change the default configuration of this register . channel data registers 16/24 bits, read-only registers, address 08h?fh, default width 16 bits, default value 8000h these registers contain the most up-to-date conversion results corresponding to each analog input channel. the 16- or 24-bit da ta width can be configured by setting the ?6/24?bit in the mode register. the relevant rdy bit in the channel status register go es high when the result is updated. the rdy bit will return low once the data register reading has begun. the rdy cdr dt rsddrs dcrs cscr 24 bits, read/write registers, address 10h?7h, default value 800000h these registers hold the particular channel zero-scale calibration coefficients. the value in these registers is used in conjun ction with the value in the corresponding channel full-scale calibration register, the adc zero-scale calibration register, and adc full-scale calibration register to scale digitally the particular channel conversion results. the value in this register is upd ated auto- matically following the execution of a channel zero-scale system calibration. the format of the channel zero-scale calibration register is a sign bit and 22 bits unsigned value. writing this register is possible in the idle mode only. see the calibration description for more details. channel full-scale calibration registers 24 bits, read/write registers, address 18h?fh, default value 200000h these registers hold the particular channel full-scale calibration coefficients. the value in these registers is used in conjun ction with the value in the corresponding channel zero-scale calibration register, the adc zero-scale calibration register, and adc full scale calibration register to scale digitally the particular channel conversion results. the value in this register is updated automati- cally following the execution of a channel full-scale system calibration. writing this register is possible in the idle mode on ly. see the calibration description for more details.
rev. 0 ?16? AD7738 channel status registers 8 bits, read-only register, address 20h?7h, default value 20h channel number these registers contain individual channel status information and some general AD7738 status information. reading the status registers can be associated with reading the data registers in the dump mode. reading the status registers is always associated w ith reading the data registers in the continuous read mode. see the digital interface description section for more details. bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic ch2 ch1 ch0 0/p0 rdy/p1 noref sign ovr default channel number 0 0 0 0 0 bit mnemonic description 7? ch2?h0 these bits reflect the channel number. this can be used for current channel identification and easier operation in the dump mode and continuous read mode. 40 /p 0 when the status option bit in the corresponding channel setup register is reset to 0, this bit is read as a zero. when the status option bit in set to 1, this bit reflects the state of the p0 output pin. 3 rdy/p1 when the status option bit in the corresponding channel setup register is reset to 0, this bit reflects the selected channel rdy bit in the adc status register. when the status option bit is set to 1, this bit reflects the state of the p1 pin whether it is configured as an input or output. 2 noref this bit indicates the reference input status. if the voltage between the refin+ and refin?pins is less than the noref trigger voltage, then the noref bit goes to a 1. 1 sign the voltage polarity at the analog input. will be 0 for a positive voltage; will be 1 for a negative voltage. 0 ovr this bit reflects either overrange or underrange on an analog input. the bit is set to 1 when the analog input voltage goes over or under the nominal voltage range. see the analog inputs extended voltage range section.
rev. 0 AD7738 ?17? channel setup registers 8 bits, read/write register, address 28h?fh, default value 00h these registers are used to configure the selected channel, its input voltage range, and set up the corresponding channel statu s register. bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic buf off com1 com0 stat. opt. enable rng2 rng1 rng0 default 0 0 0 0 0 0 0 0 bit mnemonic description 7 buf off buffer off. if reset to 0, then internal buffer is enabled. only operation with internal buffer enabled is recommended. 6, 5 com1, com0 analog input configuration. see table xi. 4 stat. opt. status option. when this bit is set to 1, the p1 bit in the status channel register will reflect the state of the p1 pin. when this bit is reset to 0, the p1 bit in the status channel register bit will reflect the channel corresponding rdy bit in the adc status register. 3 enable channel enable. set this bit to 1 to enable the channel in the continuous conversion mode. a single conversion will take place regardless of this bit value. 2? rng2? the channel input voltage range. see table xii. table xi. com1 com0 com1 com0 channel 0 0 1 1 0 ain0?incom ain0?in1 1 ain1?incom ain2?in3 2 ain2?incom ain4?in5 3 ain3?incom ain6?in7 4 ain4?incom ain0?in1 5 ain5?incom ain2?in3 6 ain6?incom ain4?in5 7 ain7?incom ain6?in7 table xii. nominal input rng2 rng1 rng0 voltage range 10 0 2.5 v 10 10 v to +2.5 v 00 0 1.25 v 00 10 v to +1.25 v 01 0 0.625 v 01 10 v to +0.625 v channel conversion time registers 8 bits, read/write register, address 30h?7h, default value 91h the conversion time registers enable or disable chopping and configure the digital filter for a particular channel. this register value affects the conversion time, frequency response, and noise performance of the adc. bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic chop fw (7-bit filter word) default 1 11h bit mnemonic description 7 chop chop enable bit. set to 1 to apply chopping mode for a particular channel. 6? fw chop = 1, single conversion or continuous conversion with one channel enabled. conversion time ( s) = (fw 128 + 248)/mclk frequency (mhz), the fw in range of 2 to 127. chop = 1, continuous conversion with two or more channels enabled. conversion time ( s) = (fw 128 + 249)/mclk frequency (mhz), the fw in range of 2 to 127. chop = 0, single conversion or continuous conversion with one channel enabled. conversion time ( s) = (fw 64 + 206)/mclk frequency (mhz), the fw in range of 3 to 127. chop = 0, single conversion or continuous conversion with two or more channels enabled. conversion time ( s) = (fw 64 + 207)/mclk frequency (mhz), the fw in range of 3 to 127.
rev. 0 ?18? AD7738 mode register 8 bits read/write register, address 38h?fh, default value 00h the mode register configures the part and determines the part? operating mode. writing to the mode register will clear the adc status register, set the rdy tdts ddt d d d cds d cntrd t c d d dd tdw t cds cdw ctctt ctwcnd cdsw cnctd cdstd sc d dwcscd wdcs cdsd ctcr d csdds d d cntrd wdcrsd d t tcdrdws wcd wcd c tcd wccd wcd s er d d d rws c c tcsc sc cc d s dcssc cctdcsc c ssc cc c ssc cc
rev. 0 AD7738 ?19? md2 md1 md0 operating mode 000 idle mode the default mode after power-on or reset. the AD7738 returns to this mode automatically after any calibration or after a single conversion. 001 continuous conversion mode the AD7738 performs a conversion on the specified channel. after the conversion is complete, the relevant channel data register and channel status register are updated, the relevant rdy bit in the adc status register is set, and the AD7738 continues converting on the next enabled channel. the AD7738 will cycle through all enabled channels until put into another mode or reset. the cycle period will be the sum of all enabled channels? conversion times, set by corresponding channel conversion time registers. 010 s ingle conversion mode the AD7738 performs a conversion on the specified channel. after the conversion is complete, the relevant channel data register and channel status register are updated, the relevant rdy bit in the adc status register is set, the rdy dddd rcse ds tdctd tcdsct ds dcssc dc dcscrdydc rdy dddd cssc d c scrdydc rdy dddd cssc d cs crdydc rdy dddd
rev. 0 ?20? AD7738 digital interface description hardware the AD7738 serial interface can be connected to the host device via the serial interface in several different ways. the cs d w cs dscdn dtw cs cs dnd t rdy d dt d w rdy n rdy t reset dw d dd td dndt tsc t d rttctd cr stt d d s cs ds r td reset d t n 0 + 32 1, which could be the data sequence 00h + ffh + ffh + ffh + ffh in a byte oriented inter face. the AD7738 also features a power-on reset with a trip point of 2 v and goes to the defined default state after power on. it is the system designer?s responsibility to prevent an unwanted write operation to the AD7738. the unwanted write operation could happen when a spurious clock appears on the sclk while the cs d tw sc dn dt cs rdy reset dnd d dd d sc s s nt c ss d dd sc dn dt cs rdy reset d dd d sc dt dr nt ds ts rs sc dn dt cs reset dnd d dd d td rd c a. b. c. figure 5. AD7738 to host device possible interface access the AD7738 registers all communications to the part start with a write operation to the communications register followed by either reading or writing the addressed register. in a simultaneous read-write interface (such as spi), write 0 to the AD7738 while reading data. figure 6 shows the AD7738 interface read sequence for the adc status register. din sclk cs dout write communications register read adc status register figure 6. the serial interface signals?register access
rev. 0 AD7738 ?21? single conversion and reading data when the mode register is being written, the adc status byte is cleared and the rdy w dc d rdy rdy trdy rdy cd c rdy cd d wdc s cds dc tdn dd c rdy csd d dn sc cs dt w rte c nctns re ster w rte de re ster rdy c nersn te red dt re ster dt dt w rte c nctns re ster sssccdr dn sc cs dt w rte c nctns re ster w rte de re ster rdy c nersn te red dt re ster cstt dt w rte c nctns re ster red cnne stts dt sssccdrd
rev. 0 ?22? AD7738 continuous conversion mode when the mode register is being written, the adc status byte is cleared and the rdy w dc cd cs rdydcsd t d t cct trdycd t rdy rdynwrdyn rdy w rdy dc dc trdy rdy c d ddc dr ccc rdynt rdy dr rdynt rdy d rdy d ccnersn ccnersn ccnersn ccnersn ccnersn strt cntns cnersn ser nterce red dt c red dt c red dt c red dt c rdy ccccrdyn rdy ccnersn ccnersn ccnersn ccnersn ccnersn red dt c red dt c strt cntns cnersn ser nterce red dt c red dt c ccccrdyn ser nterce st rt c ntns c nersn rdy ccnersn ccnersn ccnersn ccnersn ccnersn ccccndr
rev. 0 AD7738 ?23? din 48h 00h data 00h data 00h ch.stat. read ch0 da ta register read ch0 stat us 48h w rite comm. re gister sclk cs dout w rite comm. re gister w rite m ode re gister rdy 38h 00h data 00h data 00h ch.stat. re ad ch1 data re gister read ch1 stat us c onversion on ch0 complete c onversion on ch1 complete figure 12. continuous conversion ch0 and ch1, continuous read continuous read (continuous conversion) mode when the continuous rd bit in the mode register is set, the first write 48h to the communication register starts the continu- ous read mode. as shown in figure 12, subsequent accesses to the part sequentially reads the channel status and data registers of the last completed conversion without any further configuration of the communication register being required. note that the continuous conversion bit in the mode register should be set when entering the continuous read mode. note that the continuous read mode is dump mode reading of the channel status and data register regardless of the dump bit value. use the channel bits in the channel status regis ter to check/recognize which channel data is actually being shifted out. note that the last completed conversion result is being read. therefore, the rdyfn bit in the i/o port register should be 0, and reading the result should always start before the next con- version is completed. the AD7738 will stay in continuous read mode as long as the din pin is low while the cs t dcrt crdn wd t crd dnt c rt crd crctdescrtn tdd cdsc dc e td dct sdc cc cs td w t t dcnt d rc trc d tdc t dc tdcn ds cdt dc td t t c w dce t
rev. 0 ?24? AD7738 - c hannel 1 s caling time sa mpling time +channel 1 sa mpling time s ettling time multiplexer - c hannel 0 rdy s ettling time conversion time +channel 2 figure 14. multiplexer and conversion timing?continuous conversion on several channels with chopping enabled s caling time +channel 1 sa mpling time +channel 0 +channel 2 s ettling time conversion time multiplexer rdy figure 15. multiplexer and conversion timing?continuous conversion on several channels with chopping disabled multiplexer ain(+) ain(e ) + digital filter muxout adcin - modulator bu ffer - scaling arithmetic (calibrations) chop chop f mclk /2 f mclk /2 digital interface output data at the selected data rate figure 13. channel signal chain diagram with chopping enabled multiplexer, conversion, and data output timing the specified conversion time includes one or two set tling and sampling periods and a scaling time. with chopping enabled (figure 14), a conversion cycle starts with a settling time of 43 or 44 mclk cycles (~7 s with 6.144 mhz mclk) to allow the circuits following the multi plexer to settle. then the sigma-delta modulator samples the analog signals, and the digital filter processes the digital data stream. the sampling time depends on fw, i.e., on the c hannel conversion time register contents. after another settling of 42 mclk cycles (~6.8 s), the sampling time is repeated with a reversed (chopped) analog input signal. then, during the scaling time of 163 mclk cycles (~26.5 s), the two results from the digital filter are averaged, scaled using the calibration registers, and written into the channel data register. with chopping disabled (figure 15), there is only one sam pling time preceded by a settling time of 43 or 44 mclk cycles and followed by a scaling time of 163 mclk cycles. the rdy s trdydcs cs rdy cd cc n t r tc t nct t cctt n t cctt dc tt cct
rev. 0 AD7738 ?25? figure 16. typical adc frequency response normalized input frequency (input frequency conversion time) 0 0.1 10 1 gain e db e10 e20 e30 e40 e50 e60 chop = 1 a. chopping enabled normalized input frequency (input frequency conversion time) 0 0.1 1000 1 gain e db e10 e20 e30 e40 e50 e60 10 100 chop = 0 b. chopping disabled analog inputs voltage range the absolute input voltage range with input the buffer enabled is restricted from agnd + 200 mv to av dd e 300 mv, which also places restrictions on the common-mode range. care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded, otherwise there will be degradation in linearity performance. the analog inputs on the AD7738 can accept either unipolar or bipolar input voltage ranges. bipolar input ranges do not imply that the part can handle negative voltages with respect to system ground on its analog inputs. unipolar and bipolar signals on the ain(+) input are referenced to the voltage on the respective ain(e) input. for example, if aincom is 2.5 v and ch0 is configured to measure ain0 e aincom, 0 v to 1.25 v, the input voltage range on the ain0 input is 2.5 v to 3.75 v. if ch0 is config- ured to measure ain0 e aincom, 1.25 v, the input voltage range on the ain0 input is 1.25 v to 3.75 v. analog inputs extended voltage range the AD7738 output data code span corresponds to the nominal input voltage range. however, the correct operation of the adc is guaranteed within the min/max input voltage range. when the clamp bit of the mode register is set to 1, the channel data register will be digitally clamped either to all zeros or all ones when the analog input voltage goes outside the nominal input voltage range. as shown in tables xiii and xiv, when clamp = 0, the data reflect the analog input voltage outside the nominal voltage range. in this case, the sign and ovr bits in the channel status register should be considered along with the data register value to decode the actual conversion result. table xiii. input voltage range 1.25 v, 16 bits, clamp = 0 input (v) data (hex) sign ovr +1.45000 147b 0 1 +1.25008 0001 0 1 +1.25004 0000 0 1 +1.25000 ffff 0 0 +0.00004 8001 0 0 0.00000 8000 0 0 e0.00004 7fff 1 0 e1.25000 0000 1 0 e1.25004 ffff 1 1 e1.25008 fffe 1 1 e1.45000 eb85 1 1 table xiv. input voltage range 0 v to 1.25 v, 16 bits, clamp = 0 input (v) data (hex) sign ovr 1.45000 28f5 0 1 1.25004 0001 0 1 1.25002 0000 0 1 1.25000 ffff 0 0 0.00002 0001 0 0 0.00000 0000 0 0 e0.00002 0000 1 1
rev. 0 ?26? AD7738 voltage reference inputs the AD7738?s reference inputs, refin(+) and refin(e), provide a differential reference input capability. the common- mode range for these differential inputs is from agnd to av dd . the nominal reference voltage for specified operation is 2.5 v. both reference inputs feature a high impedance, dynamic load. because the input impedance on each reference input is dynamic, external resistance/capacitance combinations may result in gain errors on the part. the output noise performance outlined in tables i to vi is for an analog input of 0 v and is unaffected by noise on the reference. to obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7738. if the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7738. recommended reference voltage sources for the AD7738 in clude the adr421, ad780, ref43, and ref192. it is generally rec ommended to decouple the output of these references to further reduce the noise level. reference detect the AD7738 includes on-chip circuitry to detect if the part has a valid reference for conversions. if the voltage between the refin(+) and refin(e) pins goes below the noref trigger voltage (0.5 v typ) and the ad 7738 is performing conversion, the noref bit in the channel status register is set. i/o port the AD7738 pin sync d wsync sync d c ccd sync t sync dr t nd n dd dd dd cc enertr cn ct d dd d dd dcn t dc er t d n nc n ser nterce nd cntr c sc dn dt cs rdy reset ren ren dnd nd st syste n nts d dd tcd
rev. 0 AD7738 ?27? calibration the AD7738 provides zero-scale self-calibration, and zero and full system calibration capability, which can effectively reduce the offset error and gain error to the order of the noise. after each conversion, the adc conversion result is scaled using the adc calibration registers and the relevant channel calibra tion registers before being written to the data register. see the equa- tions shown below. for unipolar ranges: data = ((adc result e adc zs cal. reg.) adc fs reg./ 200000h e ch. zs cal. reg.) ch. fs cal. reg./200000h for bipolar ranges: data = ((adc result e adc zs cal. reg.) adc fs reg./ 400000h + 800000h e ch. zs cal. reg.) ch. fs cal. reg./ 200000h where the adc result is in the range of 0 to ffffffh. note that the channel zs calibration register has the format of a sign bit + 22 bits channel offset value. it is strongly recommended that the user does not change the adc fs register. to start any calibration, write the relevant mode bits to the AD7738 mode register. after the calibration is complete, the contents of the corresponding calibration registers are up dated, all rdy bits in the adc status register are set, the rdy d t t t dcssc tdcssc cd cd t dct dcsc t nc dcsc csc cssc cssc tscdcssc scs cdcsc sc w tc dn cd n ss c
rev. 0 c03072?0?11/02(0) printed in u.s.a. ?28? AD7738 outline dimensions 28-lead thin shrink small outline package (tssop) (ru-28) dimensions shown in millimeters 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 6.40 bsc pin 1 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ae coplanarity 0.10

▲Up To Search▲

Price & Availability of AD7738

	To Download AD7738 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .